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this is information on a product in full production. may 2012 doc id 018355 rev 5 1/67 1 STW82100B rf down converter with embedded integer-n synthesizer datasheet ? production data features high linearity: ? iip3: +25.5 dbm ? 2frf-2flo spurious rejection: 77 dbc noise figure: ? nf: 10.5 db conversion gain ? cg: 8 db rf range: 1620 mhz to 2400 mhz wide if amplifier frequency range: 70 mhz to 400 mhz integrated rf balun with internal matching dual differential integrated vcos with automatic center frequency calibration: ? loa: 1650 to 1950 mhz ? lob: 2050 to 2370 mhz embedded integer-n synthesizer ? dual modulus programmable prescaler (16/17 or 19/20) ? programmable reference frequency divider (10 bits) ? adjustable charge pump current ? digital lock detector ? excellent integrated phase noise ? fast lock time: 150 s integrated dac with dual current output supply: 3.3 v and 5 v analog, 3.3 v digital dual digital bus interface: spi and i 2 c bus (fast mode) with 3 bit programmable address (1101a 2 a 1 a 0 ) process: 0.35 m bicmos sige operating temperature range -40 to +85 o c 44-lead exposed pad vfqfpn package7x7x1.0 mm applications cellular infrastructure equipment: ? if sampling receivers ? digital pa linearization loops other wireless communication systems. description the stmicroelectronics STW82100B is an integrated down converter providing 8 db of gain, 10.5 db nf, and a very high input linearity by means of its passive mixer. embedding two wide band auto calibrating vcos and an integer-n synthesizer, the STW82100B is suitable for both rx and tx requirements for cellular infrastruc ture equipment. the integrated rf balun and internal matching permit direct 50 ohm single-ended interface to rf port. the if output is suitable for driving 200-ohm impedance filters. by embedding a dac with dual current output to drive an external pin diode attenuator, the STW82100B replaces several costly discrete components and offers a significant footprint reduction. the STW82100B device is designed with stmicroelectronics advanced 0.35 m sige process. its performance is specified over a -40 c to +85 c temperature range. table 1. device summary part number package packaging STW82100B vfqfpn-44 tray STW82100Btr vfqfpn-44 tape and reel vfqfpn-44 www.st.com
contents STW82100B 2/67 doc id 018355 rev 5 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.1 reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.2 reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.3 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.4 a and b counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.5 phase frequency detector (pfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1.6 lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.7 mute until lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.8 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.9 voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.10 output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.11 external vco buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.12 mixer and if amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1.13 dual output current dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STW82100B contents doc id 018355 rev 5 3/67 9 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 i 2 c general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.3 byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.4 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.5 single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.6 multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.7 current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2 i 2 c timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.1 data and clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.2 i 2 c start and stop timing specification . . . . . . . . . . . . . . . . . . . . . . 36 9.2.3 i 2 c acknowledge timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 i2c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3.1 i 2 c register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3.2 i 2 c register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.4 device calibration through the i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.1 vco calibration procedure (i 2 c interface) . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.2 power on sequence (i 2 c interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.3 vco calibration auto-restart procedure (i 2 c interface) . . . . . . . . . . . . . 46 10 spi digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 spi general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 spi timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2.1 data, clock and load timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.3 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3.1 spi register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3.2 spi register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.4 device calibration through the spi interface . . . . . . . . . . . . . . . . . . . . . . 53 10.4.1 vco calibration procedure (spi interface) . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.2 power on sequence (spi interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.3 vco calibration auto-restart procedure (spi interface) . . . . . . . . . . . . . 54
contents STW82100B 4/67 doc id 018355 rev 5 11 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3 diversity mode operation with same lo frequency . . . . . . . . . . . . . . . . . 58 11.4 diversity mode operation with different lo frequencies . . . . . . . . . . . . . . 59 11.5 external vco standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.6 external vco diversity mode operation with same lo . . . . . . . . . . . . . . 61 12 evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STW82100B list of tables doc id 018355 rev 5 5/67 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. down converter mixer and if amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . 15 table 7. pin diode attenuator driver (dual output current dac) electrical characteristics. . . . . . . . . 16 table 8. integer-n synthesizer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. current values for cpsel[2:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. vcoa performance against amplitude setting (frequency = 3.6 ghz) . . . . . . . . . . . . . . . . 30 table 12. vcob performance against amplitude setting (frequency = 4.3 ghz) . . . . . . . . . . . . . . . . 30 table 13. suggested cap[2:0] values for lo frequency range mixer . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. linearity performance against ifamp[1:0] configuration (typical condition) . . . . . . . . . . . . 32 table 15. i 2 c data and clock timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. i 2 c start and stop timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. i 2 c acknowledge timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. i 2 c register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20. spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21. spi register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22. application circuit component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 23. evaluation kit order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24. vfqfpn-44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
list of figures STW82100B 6/67 doc id 018355 rev 5 list of figures figure 1. STW82100B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. STW82100B pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. conversion gain against rf frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. noise figure against rf frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5. iip3 against rf frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. 2rf-2lo response against rf frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. loa (vcoa div. by 2) closed-loop phase noise at 1.8 ghz (f step = 200 khz, i cp = 2 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. lob (vcob div. by 2) closed-loop phase noise at 2.2 ghz (f step = 200 khz, i cp = 2 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. vco divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. pfd diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. vco typical sub-band characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. data validity waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15. start and stop condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. byte format and acknowledge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. i 2 c data and clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18. i 2 c start and stop timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. i 2 c acknowledge timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. i 2 c first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 21. spi input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22. spi data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 23. spi timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 24. spi first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 25. typical STW82100B application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 figure 26. standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 27. diversity mode operation with same lo frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 28. diversity mode operation with different lo frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 29. external vco standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 30. external vco diversity mode operation with same lo. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 31. vfqfpn-44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
STW82100B block diagram doc id 018355 rev 5 7/67 1 block diagram figure 1. STW82100B block diagram vdd_dac rext_dac vdd_div vdd_vco extvco_inn extvco_inp ext_pd add2 add1 add0 vdd_io vdd_pscbuf vdd_outbuf outbufn outbufp vctrl icp rext_cp vdd_cp lock_det ref_clk vdd_pll dbus_sel vdd_dig sda/data scl/clk load if_outn if_outp vdd_ifamp test2 test1 test_alc rf_ct rf_in vdd_rfesd mixdrv_ct vdd_alc vdd_mixdrv i_pindrv1 i_pindrv2 vss_alc vss_dac vss_ifamp vss_dig vss_pll vss_cp vss_pscbuf vss_io vss_vco vss_outbuf vss_div vss_mixdrv rf_vss dac if amp dbus vco mix div2 vco ref chp pfd vco buff divider divider buf drv calibrator cal_vco up dn cal_vco lo lo/2xlo ext out out lo/vco buf vss_rfesd
pin description STW82100B 8/67 doc id 018355 rev 5 2 pin description figure 2. STW82100B pin configuration vdd_dac rext_dac vdd_div vdd_vco extvco_inn extvco_inp ext_pd add2 add1 add0 vdd_io vdd_pscbuf nc nc vdd_outbuf outbufn outbufp vctrl icp rext_cp vdd_cp lock_det ref_clk vdd_pll dbus_sel vdd_dig sda/data scl/clk load nc if_outn if_outp vdd_ifamp test2 test1 test_alc rf_ct rf_in vdd_rfesd mixdrv_ct vdd_alc vdd_mixdrv i_pindrv1 i_pindrv2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STW82100B vfqfpn44
STW82100B pin description doc id 018355 rev 5 9/67 table 2. pin list pin no name description observation 1 vdd_dac dac power supply vsupply analog1= 3.3 v 2 rext_dac external resistance connection for dac - 3 vdd_div divider by 2 power supply vsupply analog1= 3.3 v 4 vdd_vco vcos and external vco buffer power supply vsupply analog1= 3.3 v 5 extvco_inn external vco (lo) negative input diversity slave mode and external vco modes; otherwise it must be connected to gnd 6 extvco_inp external vco (lo) positive input diversity slave mode and external vco modes; otherwise it must be connected to gnd 7 ext_pd hardware power down: ?0? device on; ?1? device off cmos input 8 add2 i 2 cbus address select pin cmos input 9 add1 i 2 cbus address select pin cmos input 10 add0 i 2 cbus address select pin cmos input 11 vdd_io digital io power supply vsupply digital = 3.3 v 12 vdd_pscbuf prescaler input buffer power supply vsupply analog1= 3.3 v 13 nc not connected - 14 nc not connected - 15 vdd_outbuf power supply for lo buffer vsupply analog1=3.3 v 16 outbufn lo output buffer negative output open collector @3.3 v 17 outbufp lo output buffer posit ive output open collector @ 3.3 v 18 vctrl control voltage for vcos - 19 icp pll charge pump output - 20 rext_cp external resistance connection for pll charge pump current - 21 vdd_cp power supply for charge pump vsupply analog1= 3.3 v 22 lock_det lock detector cmos output 23 ref_clk reference frequency input - 24 vdd_pll pll digital power supply vsupply analog1= 3.3 v 25 dbus_sel digital bus interface select cmos input 26 vdd_dig power supply for digital bus interface vsupply digital = 3.3 v 27 sda/data i 2 cbus /spi data line cmos bidir schmitt triggered 28 scl/clk i 2 cbus /spi clock line cmos input schmitt triggered 29 load spi load line cmos input schmitt triggered 30 nc not connected - 31 if_outn if amplifier negative output open collector @ 5 v (1)
pin description STW82100B 10/67 doc id 018355 rev 5 32 if_outp if amplifier positiv e output open collector @ 5 v (1) 33 vdd_ifamp if amplifier power supply vsupply analog1 = 3.3 v 34 test2 test input 2 test purpose only; it must be connected to gnd 35 test1 test input 1 test purpose only; it must be connected to gnd 36 test_alc test output test purpose only; it must be connected to gnd 37 rf_ct rf balun central tap - 38 rf_in rf input - 39 vdd_rfesd rf esd positive rail power supply vsupply analog1 = 3.3 v 40 mixdrv_ct mixer driver balun central tap vsupply analog2 = 5 v (1) 41 vdd_alc alc power supply vsupply analog1 = 3.3 v 42 vdd_mixdrv mixer driver power supply vsupply analog1 = 3.3 v 43 i_pindrv1 dac current output for external pin diode attenuator pmos open drain 44 i_pindrv2 dac current output for external pin diode attenuator pmos open drain 1. supply voltage @ 3.3 v in low-current mode operation table 2. pin list (continued) pin no name description observation
STW82100B absolute maximum ratings doc id 018355 rev 5 11/67 3 absolute maximum ratings table 3. absolute maximum ratings symbol parameter values unit avcc1 analog supply voltage 0 to 4.6 v avcc2 analog supply voltage 0 to 6 v dvcc digital supply voltage 0 to 4.6 v tstg storage temperature +150 c esd (electro-static discharge) hbm on pins 16, 17, 31, 32, 37, 40 0.8 kv hbm on pin 38 1 hbm on all remaining pins 2 cdm-jedec standard on pin 38 0.25 cdm-jedec standard on all remaining pins 0.5 mm 0.2
operating conditions STW82100B 12/67 doc id 018355 rev 5 4 operating conditions table 4. operating conditions symbol parameter test co nditions min typ max unit avcc1 analog supply voltage - 3.15 3.3 3.45 v avcc2 analog supply voltage - 4.75 5 5.25 v dvcc digital supply voltage - 3.15 3.3 3.45 v i cc3.3v current consumption at 3.3 v standard mode - 130 150 ma external vco standard mode - 110 130 ma diversity slave mode - 105 120 ma diversity master mode - 155 180 ma external vco diversity master mode - 140 160 ma i cc5v current consumption high current mode at 5 v - 170 195 ma low current mode at 3.3 v - 100 115 ma t a operating ambient temperature - -40 85 c t j maximum junction temperature - - 125 c ja junction to ambient package thermal resistance (1) multi-layer jedec board - 33 - c/w jb junction to board package thermal resistance (1) multi-layer jedec board - 19 - c/w jc junction to case package thermal resistance (1) multi-layer jedec board - 3 - c/w jb thermal characterization parameter junction to board (1) multi-layer jedec board - 18 - c/w jt thermal characterization parameter junction to top case (1) multi-layer jedec board - 0.3 - c/w 1. refer to jedec standard jesd 51-12 for a detailed descrip tion of the thermal resistances and thermal parameters. data here presented are referring to a mu lti-layer board according to jedec standard. t j = t a + ja * pdiss (in order to estimate t j if ambient temperature t a and dissipated power pdiss are known) t j = t b + j b * pdiss (in order to estimate t j if board temperature t b and dissipated power pdiss are known) t j = t t + j t * pdiss (in order to estimate t j if top case temperature t t and dissipated power pdiss are known)
STW82100B operating conditions doc id 018355 rev 5 13/67 t table 5. digital logic levels symbol parameter test conditions min typ max unit vil low level input voltage - - - 0.2*vdd v vih high level input voltage - 0.8*vdd - - v vhyst schmitt trigger hysteresis - 0.8 - - v vol low level output voltage - - - 0.4 v voh high level output voltage - 0.85*vdd - - v
test conditions STW82100B 14/67 doc id 018355 rev 5 5 test conditions unless otherwise specified the follo wing test conditions are applied: vsupply digital = 3.3 v vsupply analog1 = 3.3 v vsupply analog2 = 5 v f if = 150 mhz mix = 0111 t ambient = 27 c refer also to section 11: application information .
STW82100B electrical characteristics doc id 018355 rev 5 15/67 6 electrical characteristics note: vsupply digital = 3.3 v, vsupply analog1 = 3.3 v, vsupply analog2 = 5 v, f rf = 2100 mhz, f lo = 1950 mhz, t a = +25 *c, rf power = 0 dbm, unless otherwise specified. ) table 6. down converter mixer and if amplifier electrical characteristics (1) symbol parameter conditions min typ max unit f rf rf frequency - 1620 - 2400 mhz f lo lo frequency vcoa divided by 2 1650 - 1950 mhz vcob divided by 2 2050 - 2370 mhz f if if center frequency (2) f if = abs(f lo -f rf )70-400mhz cg power conversion gain rin = 50 ohm, rout = 200 ohm rfin = 0 dbm 7.5 8 8.5 db cg t power conversion gain over temperature (3) t= -40 to +85 c - 0.7 - db ip 1db input p1db high current mode - 13.5 - dbm low current mode - 8 - iip3 third-order input intercept point (4) high current mode 24.5 25.5 - dbm low current mode 18.5 19.5 - iip3 t iip3 variation over temperature (3) t= -40 to +85 c - 0.5 - db nf rf -nf lo spurious rejection at if (3) 2f rf -2f lo f rfin = -5 dbm, f if = 150 mhz -77-dbc 3f rf -3f lo f rfin = -5 dbm, f if = 150 mhz -77-dbc nf ssb noise figure high-current mode, mix = 0011 - 10.5 11 db low-current mode, mix = 0011 - 10.5 11 db - lo to if leakage 1xlo - -35 - dbm 2xlo -33 - lo to rf leakage - - -29 - dbm - rf to if isolation - - 58 - db rf rl rf return loss matched to 50 ohm - 20 - db if rl if return loss matched to 200 ohm - 25 - db - gain flatness for tx observation path (5) maximum deviation from f c over 10 mhz. for any f c within each tx observation path band. -0.05 - +0.05 db maximum deviation from f c over 30 mhz. for any f c within each tx observation path band. -0.10 - +0.10 db
electrical characteristics STW82100B 16/67 doc id 018355 rev 5 - phase flatness for tx observation path (5) maximum deviation from linear phase at f c over 10 mhz. for any f c within each tx observation path band. -0.3 - +0.3 deg maximum deviation from linear phase at f c over 30 mhz. for any f c within each tx observation path band. -0.7 - +0.7 deg - gain flatness for rx path (5) maximum ripple over a 4 mhz band. for any f c within each rx path band. --0.1 db pk-pk - phase flatness for rx path (5) maximum ripple over a 4 mhz band. for any f c within each rx path band. --0.6 deg pk-pk icc md mixer driver current consumption 3.3 v supply (pin 41, 42) - 49 - ma 5 v supply (pin 40) - 60 - ma mixer driver current consumption (low current mode) 3.3 v supply (pin 41, 42) - 20 - ma 3.3 v supply (pin 40) - 35 - ma icc ifam ifamp current consumption 3.3 v supply (pin 33) - 10 - ma 5 v supply (pin 31, 32) - 108 - ma ifamp current consumption (low current mode) 3.3 v supply (pin 33) - 6 - ma 3.3 v supply (pin 31, 32) - 55 - ma 1. all linearity and nf performances are intended at maximu m lo amplitude (lo_a[1:0]=[11]), tuning capacitors (cap[2:0]) programmed according to the selected frequency, mixer bias (mix[3:0]) set to maximize performance and the device operated in high current mode. the performances of conversi on gain, nf and linearity are intended at the sma connectors of a typical application board. 2. the if frequency range supported by the if amplifier is fr om 70 to 400 mhz. the exact if frequency range supported for a specific rf frequency c an be calculated as f if = abs(f lo -f rf ) where f lo is inside the spec ified lo frequency range. 3. guaranteed by design and characterization 4. rfin = 0 dbm/tone, rf tone spacing = 5 mhz 5. guaranteed by design table 6. down converter mixer and if amplifier electrical characteristics (1) (continued) symbol parameter conditions min typ max unit table 7. pin diode attenuator driver (dual output current dac) electrical characteristics symbol parameters conditions min typ max unit r resolution - - 10 - bit dnl differential non linearity - -0.05 - 0.05 lsb inl integral non linearity - -0.45 - 0.45 lsb i fs full scale current (1) -0.28-2.8ma - current mismatch - - - 2 % - output voltage compliance range -0-3v vr ext_dac voltage reference - - 1.19 v r ext_dac rext dac range - 10 - 100 k icc static static current consumption (iout = 0 ma; pin 1) - 2.5 - ma 1. see relationship between idac and r ext_dac in the circuit description se ction (dual output current dac)
STW82100B electrical characteristics doc id 018355 rev 5 17/67 table 8. integer-n synthesizer electrical characteristics symbol parameter conditions min typ max unit vco dividers n vco divider ratio (n) prescaler 16/17 256 - 65551 - prescaler 19/20 361 - 77836 - reference clock and phase frequency detector f ref reference input frequency - 10 19.2 200 mhz - reference input sensitivity - 0.35 1 1.5 vpeak r reference divider ratio - 2 - 1023 f pfd pfd input frequency - - - 16 mhz f step frequency step (1) prescaler 16/17 f lo / 65551 - f lo / 256 hz prescaler 19/20 f lo / 77836 - f lo / 361 hz charge pump i cp icp sink/source (2) 3bit programmable - - 5 ma v ocp output voltage compliance range - 0.4 - v dd -0.3 v - spurious (3) ---70-dbc vcos k vcoa vcoa sensitivity higher frequency range - 100 - mhz/v intermediate frequency range - 85 - mhz/v lower frequency range - 70 - mhz/v k vcob vcob sensitivity higher frequency range - 75 - mhz/v intermediate frequency range - 65 - mhz/v lower frequency range - 55 - mhz/v t lka vcoa maximum temperature variation for continuous lock (4) caltype [0] - - 125 c caltype [1] - - 125 c t lkb vcob maximum temperature variation for continuous lock (4) caltype [0] - - 95 c caltype [1] - - 125 c - vco a pushing - - 8 - mhz/v vco b pushing - - 14 - mhz/v v ctrl vco control voltage - 0.4 v dd -0.3 v - lo harmonic spurious - - -20 dbc i vco vco and vco buffer current consumption amplitude [11] (pin 4) - 35 - ma i div 2 divider by 2 consumption (pin 3) - 20 - ma
electrical characteristics STW82100B 18/67 doc id 018355 rev 5 2 x lo output buffer (test purpose only) f out frequency range - 3.3 - 4.74 ghz p out output level - - 0 - dbm rl return loss matched to 50ohm - 15 - db i 2lobuf current consumption (pin 15, 16, 17) - 26 - ma lo output buffer f out frequency range - 1.65 - 2.37 ghz p out output level - - 3 - dbm rl return loss matched to 50ohm - 14 - db i lobuf current consumption (pin 15, 16, 17) - 26 - ma external vco (lo) buffer f invco frequency range - 1.65 - 2.37 ghz p in input level - - 0 - dbm i extbuf current consumption external vco buffer (pin 4) -25 -ma pll miscellaneous i pll pll current consumption input buffer, prescaler, digital dividers, misc. (pin 24) -8 -ma i pre prescaler input buffer current consumption (pin 12) - 3 - ma i cp charge pump current consumption cpsel=[111], rext_cp = 4.7 k (pin 21) -4 -ma t lock lock up time (5) 25 khz pll bandwidth; within 1ppm of frequency error -150 -s 1. the frequency step is related to the pfd input frequency as follows: f step =f pfd /2) 2. see relationship between icp and r ext_cp in the circuit descript ion section (charge pump) 3. the level of spurs may change depending on pfd frequency, ch arge pump current, selected channel and pll loop bw. 4. when setting a specified output frequency, t he vco calibration procedure must be r un first in order to select the best subrange for the vco covering the desired frequency. once programmed at the initial temperature t 0 inside the operating temperature range (-40 o c to +85 o c), the synthesizer is able to maintain the lo ck status if the temperature drift (in either direction) is within the limit specified by t lka or t lkb , provided that the final temperature t 1 is still inside the nominal range. 5. frequency jump form 1950 to 1800 mhz; it includes the ti me required by the vco calibration procedure (7 x f pfd cycles =17.5 s with f pfd =400 khz)) table 8. integer-n synthesizer electrical characteristics (continued) symbol parameter conditions min typ max unit
STW82100B electrical characteristics doc id 018355 rev 5 19/67 table 9. phase noise performance (1) parameters conditions min. typ. max. unit in band phase noise floor, closed loop (2) normalized in band phase noise floor (lo) i cp =4 ma, pll bw = 50 khz (including reference clock contribution) --230- dbc / hz in band phase noise floor (lo) -230+20log(n)+10log(f pfd ) dbc / hz pll integrated phase noise integrated phase noise (single sided) 100 hz to 40 mhz f lo =2.200 ghz, f step =200 khz, i cp =3 ma, pll bw = 25 khz --45-dbc - 0.48 - rms loa (1650 mhz to 1950 mhz) ? open loop phase noise @ 1 khz - - -69 - dbc/hz phase noise @ 10 khz - - -95 - dbc/hz phase noise @ 100 khz - - -118 - dbc/hz phase noise @ 1 mhz - - -139 - dbc/hz phase noise @ 10 mhz - - -152 - dbc/hz phase noise floor @ 40 mhz - - -154 - dbc/hz lob (2050 mhz to 2370 mhz) ? open loop phase noise @ 1 khz - - -62 - dbc/hz phase noise @ 10 khz - - -88 - dbc/hz phase noise @ 100 khz - - -112 - dbc/hz phase noise @ 1 mhz - - -134 - dbc/hz phase noise @ 10 mhz - - -150 - dbc/hz phase noise floor @ 40 mhz - - -153 - dbc/hz 1. phase noise ssb. vco amplitude set to maximum value [ 11]. all the closed-loop perform ances are specified using a reference clock signal at 76.8 mhz with phase noise of - 144 dbc/hz @1 khz offset, -157 dbc/hz @10 khz offset and -168 dbc/hz of noise floor. 2. normalized pn = measured lo pn ? 20log(n) ? 10log(f pfd ) where n is the vco divider ratio (n=b*p+a) and f pfd is the comparison frequency at the pfd input
typical performance characteristics STW82100B 20/67 doc id 018355 rev 5 7 typical performance characteristics note: vsupply digital = 3.3 v, vsupply analog1 = 3.3 v, vsupply analog2 = 5 v, f if = 150 mhz, t a = +25 c, rf power = 0 dbm, unless otherwise specified. figure 3. conversion gain against rf frequency figure 4. noise figure against rf frequency rf frequency (mhz) conversion gain (db) noise figure (db) rf frequency (mhz)
STW82100B typical performance characteristics doc id 018355 rev 5 21/67 figure 5. iip3 against rf frequency figure 6. 2rf-2lo response against rf frequency iip3 (dbm) rf frequency (mhz) rf frequency (mhz) 2rf-2lo response (db)
typical performance characteristics STW82100B 22/67 doc id 018355 rev 5 figure 7. loa (vcoa div. by 2) cl osed-loop phase noise at 1.8 ghz (f step = 200 khz, i cp = 2 ma) figure 8. lob (vcob div. by 2) closed-loop phase noise at 2.2 ghz (f step = 200 khz, i cp = 2 ma)
STW82100B general description doc id 018355 rev 5 23/67 8 general description the STW82100B (see figure 1: STW82100B block diagram on page 7 ) consists of a high linearity passive cmos mixer with integrated rf balun, an if amplifier, a 10-bit current steering dac with dual output, and an integrated integer-n synthesizer. the synthesizer embeds 2 internal low-noise vcos with buffer blocks, a divider by 2, a low noise pfd (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a dual-modulus prescaler. the a-counter (5 bits) and b counter (12 bits) counters, in conjunction with the dual modulus prescaler p/p+1 (16/17 or 19/20), implement an n integer divider, where n = b*p+a. the device is controlled through a digital interface ( i2c bus interface or spi digital interface ). all internal devices operate with a power supply of 3.3 v except for the if amplifier output stage and the mixer driver stage operating at 5 v power supply in order to maximize the linearity performance. if the application requires a reduced linearity and noise figure performance the device is programmed in a low-current mode by using the minimum lo amplitude and the minimum biasing current in the if amplifier. in low-current mode operation the device can use only the 3.3 v power supply thus dissipating less power. 8.1 circuit description 8.1.1 reference input stage the reference input stage is shown in figure 9 . the resistor network feeds a dc bias at the f ref input while the inverter used as the frequency reference buffer is ac coupled. figure 9. reference frequency input buffer f ref vdd inverter power down buffer
general description STW82100B 24/67 doc id 018355 rev 5 8.1.2 reference divider the 10-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the pfd. the division ratio is programmed through the digital interface. 8.1.3 prescaler the dual-modulus prescaler p/p+1 takes the cm l clock from the vco buffer and divides it down to a manageable frequency for the cmos a and b counters. the modulus (p) is programmable and can be set to 16 or 19. it is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input. 8.1.4 a and b counters the a (5 bits) and b (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the refe rence division ratio. thus, the division ratio and the vco output frequency are given by the following formulae: where: f vco : vco output frequency. p: modulus of dual modulus prescaler (16 or 19 selected through the digital interface). b: division ratio of the main counter. a: division ratio of the swallow counter. f ref : input reference frequency. r: division ratio of the reference counter. n: division ratio of the pll the following points should be noted: for the vco divider to work correctly, b must be higher than a. a can take any value from 0 to 31. two pll division ratio (n) ranges are possible, depending on the value of p: ? 256 to 65551 (when p=16) ? 361 to 77836 (when p=19). nbpa + = f vco bpa + () f ref r ----------------------------------------------- =
STW82100B general description doc id 018355 rev 5 25/67 figure 10. vco divider diagram 8.1.5 phase frequency detector (pfd) the pfd takes inputs from the reference and the vco dividers and produces an output proportional to the phase error. the pfd includes a delay gate that controls the width of the anti-backlash pulse. this pulse ensures that there is no dead zone in the pfd transfer function. figure 11 is a simplified schematic of the pfd. figure 11. pfd diagram modulus prescaler 16/17 or 19/20 5-bit a counter 12-bit b counter vcobuf- vcobuf+ to p f d vdd f ref_div f vco_div vdd d delay abl down up r r q d q
general description STW82100B 26/67 doc id 018355 rev 5 8.1.6 lock detect this signal indicates that the difference between rising edges of both up and down pfd signals is found to be shorter than the fixed delay (roughly 5 ns). the lock detect signal is high when the pll is locked. the lock detector consumes current only during pll transients. 8.1.7 mute until lock this (software controlled) function shuts down the following elements until the pll achieves the lock status: rf output stage lo output buffer mixer if amplifier circuitry under this setting there is no signal at the if output stage or the lo output during a frequency jump. 8.1.8 charge pump this block drives two matched current sources, iup and idown, which are controlled respectively by the up and down pfd outputs. the nominal value of the output current is controlled by an external resistor (to be connected to the rext input pin) and the selection of one of 8 possible values by a 3-bit word. the minimum value of the output current is: imin = 2*vbg/rext_cp (vbg~1.17 v) note: the current is output on pin icp. during the vco auto calibration, icp and vctrl pins are forced to vdd/2. table 10. current values for cpsel[2:0] selection cpsel2 cpsel1 cpsel0 current value for rext=4.7 k 000i min 0.5 ma 0012*i min 1.00 ma 0103*i min 1.50 ma 0114*i min 2.00 ma 1005*i min 2.50 ma 1016*i min 3.00 ma 1107*i min 3.50 ma 1118*i min 4.00 ma
STW82100B general description doc id 018355 rev 5 27/67 figure 12. loop filter connection 8.1.9 voltage controlled oscillators vco selection within the STW82100B two low-noise vcos are integrated to cover a wide band from 1650 mhz to 1950 mhz, and from 2050 mhz to 2370 mhz after the division by 2: vco a frequency range is 3300 mhz to 3900 mhz vco b frequency range is 4100 mhz to 4740 mhz vco frequency calibration both vcos can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. these frequency ranges are intended to cover the wide band of operation and compensate for process va riations on the vco center frequency. an automatic range selection is performed when the bit sercal rises from ?0? to ?1? . the charge pump is inhibited and the pins icp and vctrl are set at a fixed calibration voltage (vcal). the frequency ranges are then tested to select the nearest one to the desired output frequency (f out = n*f ref /r) with vcal input voltage applied. after this selection, the charge pump is once again enabled and the pll performs a fine adjustment around vcal on the loop filter voltage to lock f out , thus enabling a fast settling time. two calibration algorithms are select able by setting the caltype bit. setting the caltype to ?1? guarantees the pll lock versus temperature variations. once programmed at the initial temperature, t 0 , within the operating temperature range (-40 c to +85 c), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by t lk , and provided that the final temperature, t 1 , is still inside the nominal range. setting the caltype bit to ?0? fixes vcal to the mid point of the charge pump output (vdd/2). optimum pll phase noise performance versus temperature variations with a reduced t lk i s guaranteed in this case. the t lk parameter, specific to each vco and calibration type, in the STW82100B is specified in table 8: integer-n synthesizer electrical characteristics . vdd buffer buffer vctrl c3 c2 c1 r3 r1 cal bit charge pump icp
general description STW82100B 28/67 doc id 018355 rev 5 figure 13. vco typical sub-band characteristics the sercal bit should be set to ?1? at each division ratio change. the calibration takes approximately 7 periods of the comparison fr equency and the sercal bit is automatically reset to ?0? at the end of each calibration. the maximum allowed f pfd to perform the calibration process is 1 mhz. if a higher f pfd is used the following procedure should be adopted: 1. calibrate the vco at the desired frequency with an f pfd lower than 1 mhz 2. set the a, b and r dividers ratio for the desired f pfd for calibration details refer to section 9.4.1: vco calibration procedure (i2c interface) or section 10.4.1: vco calibration procedure (spi interface) . 00000 00001 01111 11111 calibrator lock range vctrl (v) freq (hz) 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
STW82100B general description doc id 018355 rev 5 29/67 vco calibration auto-restart feature the vco calibration auto-restart feature, once activated, allows the calibration procedure to be restarted when the lock detector reports that the pll has moved to an unlock condition (trigger on ?1? to ?0? tr ansition of lock detector signal). this situation could happen if the device experiences a significant temperature variation and the caltype bit is set for optimum pll phase noise performance (caltype [0]). by enabling the vco calibration auto-restart feature (through the auto_cal bit), the device re-selects the proper vco frequency sub-range without any external user command. this feature can be enabled only when the f pfd is lower than 1 mhz. vco voltage amplitude control the voltage swing of the vcos can be adjusted over 4 levels by means of two dedicated programming bits (pll_a1 and pll_a0). th is setting trades current consumption with phase noise performances of the vco. higher amplitudes provide best phase noise while lower ones save power.
general description STW82100B 30/67 doc id 018355 rev 5 ta bl e 1 1 and ta bl e 1 2 give the current consumption and the phase noise at 1 mhz. 8.1.10 output stage the differential output signal of the synthesizer after the divider by 2 is available on pins 16 and 17. the output stage is selected by programming the pd[4:0] bits. the output stage is an open-collector structure which is able to meet different requirements over the desired output frequency range by proper connections on the pcb. see figure 27: diversity mode operation with same lo frequencies . 8.1.11 external vco buffer although the STW82100B includes two wideb and and low-noise vcos, external vco use capability is also provided. the external vco buffer can be used to manage a signal coming from an external vco in order to build a local oscillator signal by us ing the STW82100B internal synthesizer as a pll. this is only possible when external vc o standard mode or external vco diversity master mode operation are selected. see figure 29: external vco standard mode operation and figure 30: external vco diversity mode operation with same lo . if the STW82100B is operated in diversity slave mode, the external vco buffer manage the signal coming from the synthesizer output stage of another STW82100B device see figure 27: diversity mode operation with same lo frequencies and figure 30: external vco diversity mode operation with same lo . the selection of the external vco buffer is done by setting the pd[4:0] bits. the external vco signal can range from 1650 mhz to 2370 mhz and its minimum power level must be -10 dbm. table 11. vcoa performance against amplitude setting (frequency = 3.6 ghz) pll_a[1:0] current consumption (ma) pn @ 1 mhz 00 23 -127 01 24 -128 10 32 -131 11 35 -132 table 12. vcob performance against amplitude setting (frequency = 4.3 ghz) pll_a[1:0] current consumption (ma) pn @ 1 mhz 00 16 -124 01 18 -126 10 27 -128 11 30 -129
STW82100B general description doc id 018355 rev 5 31/67 8.1.12 mixer and if amplifier lo mixer driver the lo signal is fed through a driver in order to achieve the high power level needed to drive the passive mixer for maximum performance of linearity and nf. the lo mixer driver is coupled to the mixer with an integrated lo balun. the lo signal level is adjusted by means of an automatic level control loop (alc) controlled by the bits lo_a[1:0]. in low current mode the configuration lo_a[1:0]=?00? (minimum lo amplitude) should be selected and the power supply on pin 40 can be set to 3.3 v. the lo balun resonating frequency can be adjusted by means of the bits cap[2:0] in order to match the selected lo frequency. mixer a doubly balanced cmos passive mixer is internally driven by the high level lo signal in order to achieve high lineari ty and low noise performance. the rf integrated balun permits the removal of external components and it is internally matched to 50 ohms. the gate bias of the cmos devices in the mixer is programmable with 4 bits (mix[3:0]) to optimize the input matching and the gain of the signal chain. higher values of gate bias (higher decimal val ues of mix[3:0]) are suggested to maximize linearity and lower values to maximize the performance of gain and nf. table 13. suggested cap[2:0] values for lo frequency range mixer cap[2:0] lo frequency range 000 2225mhz 2370mhz 001 2100mhz 2225mhz 010 2000mhz 2100mhz 011 1900mhz 2000mhz 100 1825mhz 1900mhz 101 1750mhz 1825mhz 110 1700mhz 1750mhz 111 1650mhz 1700mhz
general description STW82100B 32/67 doc id 018355 rev 5 if amplifier the integrated if stage permits a 200-ohm load to be driven (typically a saw filter) ensuring high linearity. it is an open collector stage (pin 31, 32) and should be biased to 5 v with choke inductors. the typical output impedance is 200 ohms. the linearity performances are controlled by the bits ifamp[1:0]. in low current mode the configuration ifamp[1:0]=?00? (minimum linearity) should be selected and the open collector stage can be biased to 3.3 v with choke inductors. 8.1.13 dual output current dac the STW82100B embeds a 10-bit dual output steering current dac especially suited to drive an external pin diode attenuator. this prov ides power level calibration capability at the rf input for the tx observation path applications. the current sourced by the dac is related to the r ext_dac resistor acco rding to the following formulae (where vr ext_dac is approximately 1.19 v): with a 10 k r ext_dac the fs current is approximately 2.8 ma. table 14. linearity performance against ifamp[1:0] configuration (typical condition) ifamp[1:0] linearity performance 00 19.5 db 01 21.5 db 10 23.5db 11 25.5db idac lsb 1 2 -- - 3vr ext_dac r ext_dac ---------------------------------------- 1 64 ------ = lsb dac current idac fs 1 2 -- - 3vr ext_dac r ext_dac ---------------------------------------- 1023 64 ------------ - = full scale current
STW82100B i2c bus interface doc id 018355 rev 5 33/67 9 i 2 c bus interface the i 2 c bus interface is selected by hardware connection of the pin 25 (dbus_sel) to 0 v. data transmission from a microprocessor to the STW82100B takes place through the 2 wires (sda and scl) i 2 c-bus interface. the STW82100B is always a slave device. the i 2 c-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. the device that controls the data transfer is known as the master and the others as slaves. the master always initiates the transfer and provides the serial clock for synchronization. the STW82100B i 2 c bus supports fast mode operation (clock frequency up to 1 mhz). 9.1 i 2 c general features 9.1.1 data validity data changes on the sda line must only occur when the scl is low. sda transitions while the clock is high identify start or stop conditions. figure 14. data validity waveform sda scl data line stable change data valid data allowed
i2c bus interface STW82100B 34/67 doc id 018355 rev 5 9.1.2 start and stop conditions figure 15. start and stop condition waveform start condition a start condition is identified by a high to low transition of the data bus sda while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. stop condition a stop condition is identified by a transition of the data bus sda from low to high while the clock signal scl is stable in the hi gh state.. a stop condition terminates communications between the STW82100B and the bus master. 9.1.3 byte format and acknowledge every byte (8 bits long) transferred on the sda line must contain bits. each byte must be followed by an acknowledge bit. the msb is transferred first. an acknowledge bit indicates a successful data transfer. the transmitter, either master or slave, releases the sda bus after sending 8 bi ts of data. during the 9th clock pulse the receiver pulls the sda low to acknowledge the receipt of 8 bits of data. figure 16. byte format and acknowledge waveform scl sda start stop scl sda start msb 1 2 3 7 8 9 stop acknowledgement from receiver
STW82100B i2c bus interface doc id 018355 rev 5 35/67 9.1.4 device addressing to start the communication between the master and the STW82100B, the master must initiate with a start condition. following this, the master sends onto the sda line 8 bits (msb first) corresponding to the device select address and read or write mode. the first 7 msbs are the device address identifier, corresponding to the i 2 c-bus definition. for the STW82100B the address is set as ?1101a 2 a 1 a 0 ?, 3-bits programmable. the 8th bit (lsb) is the read or write operation bit (the rw bit is set to 1 in read mode and to 0 in write mode). after a start condition the STW82100B identifies the device address on the bus and, if matched, it acknowledge the identification on sda bus during the 9th clock pulse. 9.1.5 single-byte write mode following a start condition the master sends a device select code with the rw bit set to 0. the STW82100B gives an acknowledge and waits for the internal sub-address (1 byte). this byte provides access to any of the internal registers. after reception of the internal byte sub-address the STW82100B again responds with an acknowledge. a single-byte write to sub-address 0x00 would affect data_out[47:40], a single-byte write with sub-address 0x04 would affect data_out[15:8] and so on. 9.1.6 multi-byte write mode the multi-byte write mode can start from any internal address. the master sends the data bytes and each one is acknowledged. the master terminates the transfer by generating a stop condition. the sub-address determines the starting byte. for example, a multi-byte write with sub- address 0x01 and 4 data_in bytes affects 4 bytes starting at address 0x01 (registers at addresses 0x01, 0x02, 0x03 and 0x04 are modified). 9.1.7 current byte address read in the current byte address read mode, following a start condition, the master sends the device address with the rw bit set to 1 (no s ub-address is needed as there is only 1 byte read register). the STW82100B acknowledges this and outputs the data byte. the master does not acknowledge the received byte, but terminates the transfer with a stop condition. s 1101a 2 a 1 a 0 0ack sub-address byte ack data in ack p s 1101a 2 a 1 a 0 0ack sub-address byte ack data in ack .. data in ack p s 1101a 2 a 1 a 0 1 ack data out no ack p
i2c bus interface STW82100B 36/67 doc id 018355 rev 5 9.2 i 2 c timing specifications 9.2.1 data and clock timing specification figure 17. i 2 c data and clock waveforms 9.2.2 i 2 c start and stop timing specification figure 18. i 2 c start and stop timing waveforms table 15. i 2 c data and clock timing parameters symbol parameter min unit t cs data to clock set up time 2 ns t ch data to clock hold time 2 t cwh clock pulse width high 10 t cwl clock pulse width low 5.5 sda scl t cs t ch t cwl t cwh sda scl t start t stop
STW82100B i2c bus interface doc id 018355 rev 5 37/67 9.2.3 i 2 c acknowledge timing specification figure 19. i 2 c acknowledge timing waveforms table 16. i 2 c start and stop timing parameters symbol parameter min unit t start clock to data start time 2 ns t stop data to clock down stop time 2 table 17. i 2 c acknowledge timing parameters symbol parameter max unit t d1 ack begin delay 2 ns t d2 ack end delay 2 sda scl 8 9 t d1 t d2
i2c bus interface STW82100B 38/67 doc id 018355 rev 5 9.3 i 2 c registers STW82100B has 9 write-only registers and 1 read-only register. 9.3.1 i 2 c register summary the following table gives a short description of the write-only registers list. table 18. i 2 c register list offset register name description page 0x00 functional_mode functional mode register on page 39 0x01 b_counter b counter register on page 39 0x02 a_counter a counter register on page 40 0x03 ref_divider reference clock divider ratio register on page 40 0x04 control pll control register on page 41 0x05 mute_&_calibration mute and calibration control register on page 42 0x06 dac_control dac control register on page 42 0x07 mixer_control mixer control register on page 43 0x08 ifamp_lo_control if amplifier lo control register on page 43 0x09 read_only_register device id and calibration status register on page 44
STW82100B i2c bus interface doc id 018355 rev 5 39/67 9.3.2 i 2 c register definitions functional_mode functional mode register address: 0x00 type: w reset: 0x00 b_counter b counter register address: 0x01 type: w reset: 0x00 description: most significant bits of the b counter value 76543210 alc_pd pkd_en pd[4:0] b11 wwww [7] alc_pd : for test purpose only must be set to ?0?. (alc on) [6] pkd_en : for test purpose only must be set to ?0?. (peak detector output on pin 36 off) [5:1] pd[4:0] : bits used to select different functional modes for the STW82100B according to the following table 00000: (0 decimal) power down mode 00001: (1 decimal) standard mode vcoa (vcoa and rx chain on) 00010: (2 decimal) standard mode vcob (vcob and rx chain on) 00011: (3 decimal). diversity slave mode (e xtvco/lo input buffer and rx chain on; internal synthesizer off) 00100: (4 decimal) diversity master mode vcoa (vcoa, rx chain and lo output buffer on) 00101: (5 decimal) diversity master mode vcob (vcob, rx chain and lo output buffer on) 00110: (6 decimal) external lo standard mode (rx chain on; pll and extvco/lo input buffer on) 00111: (7 decimal) external lo diversity master mode (rx chain on; pll, extvco/lo input buffer and lo output buffer on) [0] b11 : b counter value (bits b[ 10:0] in the b_counter and a_counter registers) 76543210 b[10:3] w [7:0] b[10:3] : b counter value (bit b11 in the functio nal_mode register, bi ts b[2:0] in the a_counter register)
i2c bus interface STW82100B 40/67 doc id 018355 rev 5 a_counter a counter register address: 0x02 type: w reset: 0x00 description: least significant bits of the b-counter value. a-counter value. ref_divider reference clock divider ratio register address: 0x03 type: w reset: 0x00 description: most significant bits of the reference clock divider ratio value. 76543210 b[2:0] a[4:0] w w [7:5] b[2:0] : b counter value (bit b11 in the functional_mode register, bits b[10:3] in the b_counter register). [4:0] a[4:0] : a counter value 76543210 r[9:2] w [7:0] r[9:2] : reference clock divider ratio (bits r[1:0] in the control register)
STW82100B i2c bus interface doc id 018355 rev 5 41/67 control pll control register address: 0x04 type: w reset: 0x00 description: least significant bits of the reference clock divider ratio value and pll control bits. 76543210 [r1:0] pll_a[1:0] cpsel[2:0] psc_sel ww ww [7:6] r[1:0] : reference clock divider ratio (bits r[9:2] in the ref_divider register) [5:4] pll_a[1:0] : vco amplitude [3:1] cpsel[2:0] : charge pump output current [0] psc_sel : prescaler modulus select (?0? for p=16, ?1? for p=19) the lo output frequency is programmed by setting the proper value for a, b and r according to the following formula : where d r equals 0.5 (vcos output frequency divided by 2) and p is the selected prescaler modulus f lo d r bpa + ? () f ref r --------- - ?? =
i2c bus interface STW82100B 42/67 doc id 018355 rev 5 mute_&_calibration mute and calibration control register address: 0x05 type: w reset: 0x00 description: for test purposes only dac_control dac control register address: 0x06 type: w reset: 0x00 description: most significant bits of the dac control word 76543210 caltype sercal selextcal mute_en mute_type mute_loout_en mute_mix_en mute_ifamp_en wwwwwwww [7] caltype : calibration algorithm selection 0: standard calibration to optimize the phase noise versus temperature 1: enhanced calibration to maximize the tlk range [6] sercal : 1: starts the vco auto-calibration (automatic ally reset to ?0? at the end of calibration) [5] selextcal : test purpose only; must be set to ?0? [4] mute_en : 0: mute function disabled 1: mute function enabled [3] mute_type : must be set to '1' while the mute f unction is enabled (mute the if output on unlock state) [2] mute_loout_en : to be set to ?1? to mute the lo output buffer [1] mute_mix_en : to be set to ?1? mute the mixer circuitry [0] mute_ifamp_en : to be set to '1' to mute the if amplifier circuitry 76543210 dac[9:2] w [7:0] dac[9:2] : dac input word for dac current control (bits dac[1:0] in the mixer_control register).
STW82100B i2c bus interface doc id 018355 rev 5 43/67 mixer_control mixer control register address: 0x07 type: w reset: 0x00 description: least significant bits of dac control word and mixer control bit fields ifamp_ lo_control if ampl ifier lo control register address: 0x08 type: w reset: 0x00 76543210 dac[1:0] mix[3:0] pd_dac cal_autostart_en wwww [7:6] dac[1:0] : dac input word for dac current control (bits da c[9:2] in the dac_control register) [5:2] mix[3:0] : mixer bias control value [1] pd_dac : dac power down [0] cal_autostart_en : vco calibration auto-restart enable (?1? active), permits to automatically restart the vco calibrat ion procedure in case of pll unlock 76543210 ifamp[1:0] cap[2:0] lo_a[1:0] lpmux_en wwww [7:6] ifamp[1:0] : power consumption/linearity control [5:3] cap[2:0] : tuning capacitors control [2:1] lo_a[1:0] : lo amplitude control [0] lpmux_en : for test purpose only (low power mode for mux). must be set to ?0?
i2c bus interface STW82100B 44/67 doc id 018355 rev 5 read-only register dev ice id and calibra tion status register address: 0x09 type: r reset: 0x00 description: this register is automatically addressed in the ?current byte address read mode? 76543210 id[1:0] lock_det intcal[4:0] rr r [7:6] id[1:0] : device identification ?00? for STW82100B [5] lock_det : ?1? when pll is locked [4:0] intcal[4:0] : internal value of the vco calibration control word
STW82100B i2c bus interface doc id 018355 rev 5 45/67 9.4 device calibration through the i 2 c interface 9.4.1 vco calibration procedure (i 2 c interface) the calibration of the vco center frequency is activated by setting the sercal bit of the mute & calibration register to ?1?. to program the device ensuring a correct vco calibration, the following procedure is required before every channel change: 1. program all the registers using a multi-byte write sequence with the desired setting: ? functional mode ? b and a counters ? r counter ? vco amplitude ? charge pump ? prescaler modulus ?dac ? mixer and lo control ? all bits of the mute & calibrat ion register (0x05) set to ?0?. 2. program the mute & calibration register using a single-byte write sequence (sub- address 0x05) with the sercal bit set to ?1?. the maximum allowed pfd frequency (f pfd ) to perform the calibration process is 1 mhz. if the desired f pfd is higher than 1 mhz the following steps are needed: 3. perform all the step of the above calibration procedure programming the desired vco frequency with a proper setting of r, b and a counter so that f pfd results lower than 1mhz. 4. once calibration is completed, program a ll the registers by using a multi-byte write sequence (functional mode, b and a counters, r counter, vco amplitude, charge pump, prescaler modulus, dac, mixer and lo control) with the proper settings for the desired vco and pfd frequencies. 9.4.2 power on sequence (i 2 c interface) at power-on the device is configured in power-down mode. in order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed: 1. power up the device 2. provide the reference clock 3. implement the first programming sequence with a proper delay time between the stop condition of the multi-byte write sequence and that of the single-byte write sequence (see figure 20 ). the t delay value must respect the following condition: f ref is the reference clock frequency. t delay 1023 1 f ref --------- - >
i2c bus interface STW82100B 46/67 doc id 018355 rev 5 figure 20. i 2 c first programming timing 9.4.3 vco calibration auto-restart procedure (i 2 c interface) the vco calibration auto-restart feature is enabled in two steps: 1. set the desired frequency ensuring vco calibration procedure as described above ( section 9.4.1 ). 2. program the mixer_control register (sub-address 0x07) using a single-byte write sequence with the cal_autostart_en bit set to '1' while keeping the others unchanged. start start stop stop clk data msb lsb msb lsb multi-byte sequence single-byte sequence tdelay > 1023/f ref
STW82100B spi digital interface doc id 018355 rev 5 47/67 10 spi digital interface 10.1 spi general features the spi digital interface is selected by hardware connection of the pin 25 (dbus_sel) to 3.3 v. the STW82100B ic is programmed by means of a high-speed serial-to-parallel interface with write option only. the 3-wires bus can be clocked at a frequency as high as 100 mhz to allow fast programming of the registers containing the data for rf ic configuration. the programming of the chip is done through serial words with whole length of 26 bits. the first 2 msb represent the address of the registers. the others 24 lsb represent the value of the registers. each data bit is stored in the internal shift register on the rising edge of the clock signal. on the rising edge of the load signal the outputs of the selected register are sent to the device. figure 21. spi input and output bit order last data load 1 2 23 24 25 (msb) load #4 reg. #0 reg. #1 reg. #4 a1 address bit sent (lsb) 0 decoder 00 (lsb)
spi digital interface STW82100B 48/67 doc id 018355 rev 5 figure 22. spi data structure a1 a0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address data for register (24 bits) msb lsb note: msb is sent first table 19. address decoder and outputs address outputs a1 a0 databits d23-d0 n o name function 0 0 24 0 st1 dac, mixer, tuning capacitors, lo_amplitude 01 24 1st2 reference divider, vco amplitude, vco calibration, charge pump current, prescaler modulus, mute functions 1 0 24 2 st3 functional modes, vco dividers 1 1 24 3 st4 reserved
STW82100B spi digital interface doc id 018355 rev 5 49/67 10.2 spi timing specification 10.2.1 data, clock and load timing figure 23. spi timing waveforms data clock load msb lsb msb - 1 t clk t clk_loadr t load t clk_loadf t setup t hold table 20. spi timing parameters parameter description min. typ. max. unit t setup data to clock setup time 1 - - ns t hold data to clock hold time 0.5 - - ns t clk clock cycle period 10 - - ns t load load pulse width 3 - - ns t clk_loadr clock to load rising edge 0.6 - - ns t clk_loadf clock to load falling edge 2.5 - - ns
spi digital interface STW82100B 50/67 doc id 018355 rev 5 10.3 spi registers 10.3.1 spi register summary 10.3.2 spi register definitions st1 spi register 1 address: 0x00 type: w reset: 0x00 table 21. spi register list offset register name description page 0x00 st1 spi register 1 on page 50 0x01 st2 spi register 2 on page 51 0x10 st3 spi register 3 on page 52 23222120191817161514131211109876543210 dac[9:0] mix[3:0] pwd_dac cal_autostart_en if[1:0] cap[2:0] lo_a[1:0] lpmux_en wwwwwwww [23:14] dac[9:0] : dac input word [13:10] mix[3:0] : mixer bias control [9] pwd_dac : dac power down [8] cal_autostart_en : vco calibration auto-restart enable [7:6] if[1:0] : power consumption/linearity control [5:3] cap[2:0] : tuning capacitors control [2:1] lo_a[1:0] : lo amplitude control [0] lpmux_en : for test purpose only. must be set to ?0?
STW82100B spi digital interface doc id 018355 rev 5 51/67 st2 spi register 2 address: 0x01 type: w reset: 0x00 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r[9:0] pll_a[1:0] cpsel[2:0] psc_sel cal_type sercal selextcal mute_en mute_type mute_loout_en mute_mix_en mute_ifamp_en w w w wwwwwwwww [23:14] r[9:0] : reference clock divider ratio [13:12] pll_a[1:0] : vco amplitude control [11:9] cpsel[2:0] : charge pump output current control [8] psc_sel : prescaler modulus select (?0? for p=16, ?1? for p=19) [7] cal_type : calibration algorithm selection 0: standard calibration to optimize the phase noise versus temperature 1: enhanced calibration to maximize the tlk range [6] sercal : at ?1? starts the vco auto-calibration (automat ically reset to ?0? at the end of calibration) [5] selextcal : test purpose only. must be set to ?0? [4] mute_en : 0: mute function disabled 1: mute function enabled [3] mute_type : must be set to '1' while the mute function is enabled (mute the if output on unlock state) [2] mute_loout_en : to be set to ?1? to mute the lo output buffer [1] mute_mix_en : to be set to ?1? to mute the mixer circuitry [0] mute_ifamp_en : to be set to ?1? to mute the if amplifier circuitry
spi digital interface STW82100B 52/67 doc id 018355 rev 5 st3 spi register 3 address: 0x10 type: w reset: 0x00 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 alc_pd pkd_en pd[4:0] b[11:0] a[4:0] ww w w w [23] alc_pd : test purpose only; must be set to ?0? (alc on) [22] pkd_en : for test purpose only; must be set to ?0? [21:17] pd[4:0] : 00000: (0 decimal) power down mode 00001: (1 decimal) standard mode vcoa (vcoa and rx chain on) 00010: (2 decimal) standard mode vcob (vcob and rx chain on) 00011: (3 decimal). diversity slave mode (e xtvco/lo input buffer and rx chain on; internal synthesizer off) 00100: (4 decimal) diversity master mode vcoa (vcoa, rx chain and lo output buffer on) 00101: (5 decimal) diversity master mode vcob (vcob, rx chain and lo output buffer on) 00110: (6 decimal) external lo standard mode (rx chain on; pll and extvco/lo input buffer on) 00111: (7 decimal) external lo diversity master mode (rx chain on; pll, extvco/lo input buffer and lo output buffer on) [16:5] b[11:0] : b counter bits [4:0] a[4:0] : a counter bits
STW82100B spi digital interface doc id 018355 rev 5 53/67 10.4 device calibration through the spi interface 10.4.1 vco calibration pr ocedure (spi interface) the calibration of the vco center frequency is activated by setting to ?1? the sercal bit (st2 register bit [6]). in order to program properly the device while ensuring the vco calibration, the following procedure is required before every channel change: 1. program the st1 register with the desired setting (dac, mixer, lo control) 2. program the st3 register with the desired setting (functional mode, b and a counters) 3. program the st2 register with the desired setting (r counter, vco amplitude, charge pump, prescaler modulus) and sercal bit set to ?1? the maximum allowed pfd frequency (f pfd ) to perform the calibration process is 1 mhz; if the desired f pfd is higher than 1 mhz the following steps are needed: 4. perform all the steps of the above calibration procedure programming the desired vco frequency with a proper setting of r, b and a counter so that f pfd results lower than 1 mhz. 5. once calibration is completed program the device with the proper setting for the desired vco and pfd frequencies according to the following steps: a) program the st3 register with the desired setting (functional mode, b and a counters) b) program the st2 register with the desired setting (r counter, vco amplitude, charge pump, prescaler modulus) with the sercal bit set to ?0?. 10.4.2 power on sequenc e (spi interface) at power-on the device is configured in power-down mode. in order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed: 1. power up the device 2. provide the reference clock 3. implement the first programming sequence with a proper delay time between the st3 and st2 load rising edges (see figure 24 ). the t delay value must respect the following condition: f ref is the reference clock frequency. t delay 1023 1 f ref --------- - >
spi digital interface STW82100B 54/67 doc id 018355 rev 5 figure 24. spi first programming timing 10.4.3 vco calibration auto-rest art procedure (spi interface) the vco calibration auto-restart feature is enabled in two steps: 1. set the desired frequency ensuring vco calibration as described in section 10.4.1 . 2. program the st1 register with the cal_autostart_en bit set to '1' while keeping unchanged the others. data load st3 st2 msb msb-1 lsb lsb-1 msb msb-1 lsb lsb-1 t delay > 1023/f ref
STW82100B application information doc id 018355 rev 5 55/67 11 application information 11.1 application circuit figure 25. typical STW82100B application circuit c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3 1 2 3 4 5 6 7 8 9 10 11 vdd_io add0 add1 add2 ext_pd extvco_inp extvco_inn vdd_vco vdd_div rext_dac vdd_dac 3.3v_ln4 rf_in c19 3.3v_ln1 3.3v_ln3 3.3v_ln2 c15 c16 c17 5v_2 l3 l4 c18 u3 if_out 1 2 3 4 5 6 nc c14 c13 c12 r10 r9 r8 3.3v_ln2 load slc/clk sda/data 3.3v_ln2 spi i2c c11 ref_clk r7 3.3v_ln1 r6 lock_det 3.3v_ln1 r2 r3 l1 l2 c6 c7 r4 c9 c8 r5 c10 1 2 3 4 5 6 x5 x6 x7 x8 u2 nc 3.3v_ln1 3.3v_ln1 3.3v_ln1 external vco x1 x2 x3 x4 u1 nc c4 c5 3.3v_ln1 lo_output 12 13 14 15 16 17 18 19 20 21 22 vdd_pscbuf nc nc vdd_outbuf outbufn outbufp vctrl icp rext_cp vdd_cp lock_det 33 32 31 30 29 28 27 26 25 24 23 vdd_ifamp if_outp if_outn nc load slc/clk sda/data vdd_dig dbus_sel vdd_pll ref_clk 44 43 42 41 40 37 38 39 36 35 34 i_pindrv2 i_pindrv1 vdd_mixdrv vdd_alc mixdrv_ct vdd_rfesd rf_in rf_ct test_alc test1 test2 vfqfpn-44 1 2 3 4 5 6 5v_1 r1
application information STW82100B 56/67 doc id 018355 rev 5 note: 1 for optimum performance a low-noise 3.3 v power supply must be used. 2 the 3.3 v and 5 v power supplies are split in order to maximize the isolation between rf, lo, if and digital sections. table 22. application circuit component values designation quantity description supplier c1, c15 2 4.7 f capacitors cog (0402) murata manufacturing co., ltd c2, c11 2 1 nf capacitors cog (0402) c3 1 10 pf capacitor cog (0402) c4,c5 2 3.6 pf capacitors cog (0402) c6, c7, c19 3 6.8 pf capacitors cog (0402) c8 1 270 pf capacitor cog (0402) c9 1 2.7 nf capacitor cog (0402) c10 1 68 pf capacitor cog (0402) c12, c13, c14 3 15 pf capacitors cog (0402) c16 1 100 nf capacitor cog (0402) c17 1 100 pf capacitor cog (0402) c18 1 180 pf capacitor cog (0402) r1, r8, r9, r10 4 100 ohm resistors (0402) - r2, r3, r7 3 51 ohm resistors (0402) - r4 1 2.2 kohm resistor (0402) - r5 1 8.2 kohm resistor (0402) - r6 1 4.7 kohm resistor (0402) - u1 1 balun jti - 2450bl15b100 johanson technology u2 1 balun jti - 1600bl15b100 u3 1 balun adt4-5wt mini circuits x1, x8 2 3.3 nh inductors cs (0402) coilcraft, inc x2 1 1.2 pf capacitor cog (0402) murata manufacturing co., ltd x3 1 0 ohm resistor (0402) - x4 0 nc - x5 1 1.6 pf capacitor cog (0402) murata manufacturing co., ltd x6 1 3.9 nh inductor cs (0402) coilcraft, inc x7 1 2 pf capacitor cog (0402) murata manufacturing co., ltd l1, l2 2 3.7 nh inductors hq (0402) coilcraft, inc l3, l4 2 220 nh inductors cs (1206)
STW82100B application information doc id 018355 rev 5 57/67 11.2 standard mode operation the STW82100B can be used in standard mode for both rx path and tx observation path (rx chain on and synthesizer on). in such a case the 10-bit internal dac can drive an external pin diode attenuator in order to calibrate the signal level at the input of the device. figure 26. standard mode operation rf_in2 i_pindrv1 i_pindrv2 rf_in rf_vss rf_ct mixdrv_ct dac rext_dac mix div2 STW82100B rf_in drv 5v if amp dbus vco cal_vco buf dbus_sel sda/data scl/clk load lock_det 4:1 if_out 50 5v rext_cp calibrator ref_clk chp pfd up dn pll icp vco cal_vco vctrl buff if_outp if_outn
application information STW82100B 58/67 doc id 018355 rev 5 11.3 diversity mode operatio n with same lo frequency the STW82100B supports the diversity mode with the same lo frequency by using one STW82100B in master mode (rx chain on, synthesizer on and lo output buffer on) and the other in slave mode (rx chain on, synthe sizer off and ext vco/lo buffer on). this operation mode is suitable for antenna diversity. figure 27. diversity mode operat ion with same lo frequencies 4:1 if_m 50 5v if_outp if_outn if amp dbus dbus_sel sda/data scl/clk load rf_in rf_vss rf_ct rf_in_m 5v div2 buf lock_det rext_cp ref_clk chp pfd up dn pll icp vco cal_vco vctrl buff vco calibrator mixdrv_ct mix drv STW82100B master mix drv dbus rf_in rf_ct rf_in_s 100 4:1 if_s 50 if_outp if_outn STW82100B slave if amp 5v dbus_sel sda/data scl/clk load extvco_inn mixdrv_ct 5v outbufp outbufn 3.3v lo out extvco_inp 50 50 ext lo/vco buf rf_vss to dac cal_vco
STW82100B application information doc id 018355 rev 5 59/67 11.4 diversity mode operation with different lo frequencies the STW82100B is particularly suitable for diversity schemes using different lo frequencies such as the interferer diversit y. in these schemes two STW82100Bs are used, each one set in standard mode and with different lo frequencies. figure 28. diversity mode operation with different lo frequencies 4:1 if_out1 50 5v if_outp if_outn if amp dbus dbus_sel sda/data scl/clk load rf_in rf_vss rf_ct rf_in1 5v div2 buf lock_det rext_cp ref_clk chp pfd up dn pll icp vco cal_vco vctrl buff vco cal_vco calibrator mixdrv_ct mix drv STW82100B master 4:1 if_out2 50 5v if_outp if_outn if amp dbus dbus_sel sda/data scl/clk load rf_in rf_vss rf_ct rf_in2 5v div2 buf lock_det rext_cp ref_clk chp pfd up dn pll icp vco cal_vco vctrl buff vco cal_vco calibrator mixdrv_ct mix drv STW82100B diversity lo1 lo2
application information STW82100B 60/67 doc id 018355 rev 5 11.5 external vco standard mode operation the STW82100B can be used in ext vco mode for both rx path and tx observation path (rx chain on, synthesizer on, ext vco/lo buffer on and with an external vco). in such a case the 10-bit internal dac can drive an external pin diode attenuator in order to calibrate the signal level at the input of the device. figure 29. external vco standard mode operation rf_in2 i_pindrv1 i_pindrv2 rf_in rf_vss rf_ct mixdrv_ct dac rext_dac mix STW82100B rf_in drv 5v if amp dbus buf dbus_sel sda/data scl/clk load lock_det 4:1 if_out 50 5v rext_cp ref_clk chp pfd up dn pll icp ext if_outp if_outn external vco extvco_inp extvco_inn lo/vco buf
STW82100B application information doc id 018355 rev 5 61/67 11.6 external vco diversity mode operation with same lo the STW82100B can be used in diversity mode using one STW82100B in master mode (rx chain on, synthesizer on, ext vco/lo buffer on, lo output buffer on and with an external vco) and the other one in slave mode (rx chain on, synthesizer off and ext vco/lo buffer on). figure 30. external vco diversity mode operation with same lo mix drv dbus rf_in rf_ct rf_in_s 100 4:1 if_s 50 if_outp if_outn STW82100B slave if amp 5v dbus_sel sda/data scl/clk load extvco_inn mixdrv_ct 5v extvco_inp ext lo/vco buf rf_vss rf_in rf_vss rf_ct mixdrv_ct mix STW82100B master rf_in_m drv 5v if amp dbus buf dbus_sel sda/data scl/clk load lock_det 4:1 if_m 50 5v rext_cp ref_clk chp pfd up dn pll icp vco buff if_outp if_outn external vco extvco_inp extvco_inn outbufp outbufn lo/2xlo out 50 50 3.3v to dac
evaluation kit STW82100B 62/67 doc id 018355 rev 5 12 evaluation kit an evaluation kit can be delivered upon request, including the following: evaluation board gui (graphical user interface) to program the device pllsim software for pll loop filter design and noise simulation when ordering, please specify the following order code: table 23. evaluation kit order code part number description STW82100B-evb STW82100B evaluation kit, 1.6 to 2.4 ghz rf frequency range
STW82100B package mechanical data doc id 018355 rev 5 63/67 13 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. figure 31. vfqfpn-44 package outline
package mechanical data STW82100B 64/67 doc id 018355 rev 5 note: 1 vfqfpn stands for thermally enhanced very thin fine pitch quad flat package no lead. very thin: a=1.00 max. 2 details of terminal 1 identifier are optional but must be located on the top surface of the package by using either a mold or marked features. table 24. vfqfpn-44 package dimensions symbol dimensions in mm min typ max a 0.80 0.90 1.00 a1 - 0.02 0.05 a2 - 0.65 1.00 a3 - 0.200 - b 0.18 0.25 0.30 d 6.85 7.00 7.15 d1 - 6.750 - d2 3.80 3.90 4.00 d3 - 4.90 - e 6.85 7.00 7.15 e1 - 6.750 - e2 3.80 3.90 4.00 e3 - 4.90 - e - 0.50 - l 0.35 0.55 0.75 p--0.60 k (degree) - - 12 ddd - - 0.08
STW82100B revision history doc id 018355 rev 5 65/67 14 revision history table 25. document revision history date revision changes 14-jan-2011 1 first release 07-mar-2011 2 corrected cover-page description paragraph tag ta b l e 1 1 and ta b l e 1 2 : ? corrected introductory sentence ? aligned titles with corporate rules 29-jun-2011 3 corrected rf range on cover page and in table 6: down converter mixer and if amplifier electrical characteristics updated description of bitfield mute_type in mute and calibration control register removed section 4.4.1: default configuration added section 9.4.2: power on sequence (i2c interface) updated figure 23: spi timing waveforms updated table 20: spi timing parameters updated description of bitfield mute_type in spi register 2 updated description of bitfield pd[4:0] in spi register 3 removed section 5.4.1: default configuration added section 10.4.2: power on sequence (spi interface) 10-jan-2012 4 removed ?preliminary data? tags from cover page. table 3 moved to new section 3: absolute maximum ratings section 2.1 becomes section 4: operating conditions secction 2.2 becomes section 5: test conditions section 2.3 becomes section 6: electrical characteristics table 3: absolute maximum ratings pins 31 and 32 changed from 0.7 to 0.8 kv esd rating. table 4: operating conditions updated current consumption: ?i cc3.3v . updated typical values for diversity master mode and external vco diversity master mode. added maximum values. ?i cc5v . added maximum values. section 6: electrical characteristics . added note about vsupply, rf frequency range, ambient temperature and rf power conditons. table 6: down converter mixer and if amplifier electrical characteristics : ? added max value for cg ? added min values for iip3 ? modified typical value of nf rf -nf lo at 3f rf -3f lo f rfin = -5 dbm, f if = 150 mhz condition. ? modified lo to if leakage typical value ? modified if rl typical value ? modified icc md typical value on 3.3 v supply (pin 41, 42)
revision history STW82100B 66/67 doc id 018355 rev 5 10-jan-2012 4 table 8: integer-n synthesizer electrical characteristics updated: ?k vcoa and k vcob value ? t lk split into t lk a and t lk b (for vcoa and vcob). specified as maximum values. ?i2 lobuf, i lobuf, i pll and i pre values ? added table footnote 4 table 9: phase noise performance updated values of: ? integrated phase noise (single sided) 100 hz to 40 mhz ? loa open-loop phase noise @ 1 khz and 10 khz ? lob open-loop phase noise @ 1 khz and 100 khz added section 7: typical performance characteristics . modified sub-sections; ? vco frequency calibration ? vco calibration auto-restart feature updated description of bitf ield caltype in registers ? mute_&_calibration ? st2 added section 12: evaluation kit . 10-may-2012 5 corrected rf range lower value on cover page. replaced occurrences of ?sti register ? with ?spi register? in section headers: ? section 10.3: spi registers ? section 10.3.1: spi register summary ? section 10.3.2: spi register definitions . table 25. document revision history (continued) date revision changes
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